Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work

Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime

Yield Model Characterization for Analogue Integrated Circuit Using Pareto-Optimal Surface

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work

Optimal Sizing of Configurable Devices to Reduce Variability in Integrated Circuits

This paper describes a systematic approach that facilitates yield improvement of integrated circuits at the post-manufacture stage. A new Configurable Analogue Transistor (CAT) structure is presented that allows the adjustment of devices after manufacture. The technique enables both performance and yield to be improved as part of the normal test process. The optimal sizing of the inserted CAT devices is crucial to ensure the greatest improvement in yield and this paper considers this challenge in detail. An analysis and description of the underlying theory of the sizing problem is given along with examples of incorrect sizing. Guidelines to achieve optimal CAT sizing are proposed, and results are provided to demonstrate the overall effectiveness of the CAT approach

Frequency Dependent Model of Leakage Inductance for Magnetic Components

Theoretical methods for the calculation of winding losses with respect to frequency have been well documented, but the variation in leakage inductance of magnetic components due to frequency has been less well addressed. In this paper Dowell’s well-known theoretical approach is tested using measurements and finite element analyses. The results presented show deficiencies in the accuracy of models generated using Dowell’s approach and highlight the trade-offs between model complexity, simulation time and accuracy when the finite element analysis method is applied. An alternative behavioral model is presented which models the frequency variation in leakage inductance accurately, is easy to characterize from simple measurements or calculations and is robust

A Geometric Algebra Co-Processor for Color Edge Detection

This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA) co-processor implemented on an Application Specific Integrated Circuit (ASIC). GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations

Switched-current filters and phase-locked loops : methods and tools

The switched-current (SI) technique has started  a new era in analogue sampled-data signal processing where the benefit of requiring no linear floating capacitors and the suitability for low-voltage operation facilitates mixed-signal design on a standard digital CMOS process.  This thesis considers the analysis, design automation and realisation of two fundamental analogue blocks, filters and phase-locked loops (PLLs), using SI technology. A systematic design flow, from specification to layout, for SI filters employing the wave synthesis technique is presented.  A key feature of the flow is a novel power-aware scaling procedure which simultaneously reduces the filter power consumption and total harmonic distortion.  A computer aided design (CAD) methodology called AutoSIF has been developed to automate the filter design flow and facilitate rapid generation of SI wave filter circuits.  PLLs are employed in numerous applications ranging from clock recovery to demodulation and frequency synthesis.  Despite the possible advantages of applying the SI technique to PLLS, there has been very little research in this area.  This thesis describes the methodical design of SL PLLs and proposes a novel 2nd over architecture that does not require a separate phase detector, leading to a more compact implementation than conventional approaches.  Theoretical analysis and transistor level design procedures are presented for the proposed PLL architecture and a further CAD methodology, AutoPLL, has been developed to automate and support the associated design flow. Simulation results based on foundry BSim3v3 models are provided for the designed SI filters and PLLs.  To analyse the practical performance of the power-aware filter design flow, a prototype chip has been fabricated and measured results show close agreement with theoretical analysis and simulation.  Two PLL case studies are presented including a 10MHz frequency shift keying (FSK) demodulator and 500 MHz frequency synthesiser which demonstrate that the proposed SI PLL architecture is capable of producing low power designs of comparable performance to the commercial state of the art.</p